Marvell Technology Falls Over 3%. SemiAnalysis Says Co-Packaged Optics (CPO) Mass Production May Be Delayed to 2029, Nvidia Rubin Will Still Use All-Copper Solution.

TradingKey - On July 10, Eastern Time, Marvell Technology ( MRVL )'s stock price took a hit, down 3.38% to $235 as of press time. It is reported that SemiAnalysis founder Dylan Patel stated that the large-scale implementation of co-packaged optics (CPO) might be delayed to late 2028 or 2029.

[Source: TradingView]

Dylan Patel pointed out that current manufacturing yields, chip designs, and supply chain maturity have not yet met the standards for large-scale deployment. Meanwhile, Nvidia's Rubin and its successor architecture Feynman will still utilize an all-copper solution, meaning CPO on the GPU side will have to wait for several generations of chip iterations.

He believes that late 2028 to 2029 is when the large-scale mass production of CPO will truly begin.

He stated that SemiAnalysis just released a report to institutional subscribers last week, expressing a more bullish outlook on copper cables and non-CPO optical solutions in the medium term. Design changes in some downstream chips (such as the removal of the 800V design in Rubin Ultra's Kyber) have further delayed the rollout of CPO. As a result, copper cable connector companies like Amphenol will benefit more than expected.

While CPO represents a long-term trend and copper cables will eventually be replaced in the long run, the timeline for this process has been pushed back. Therefore, copper cables still present significant growth opportunities in the short-to-medium term.

Just a month ago, Marvell Technology's stock surged over 32% in a single day, fueled by an endorsement from Nvidia CEO Jensen Huang. At Computex Taipei, Huang stated that Marvell would grow into the next trillion-dollar market cap company.

He noted that under the computing power architecture for large model training, a single chip can no longer bear the massive computing demands, and tasks must be split for distributed execution across clusters consisting of thousands of chips. The high-speed data-sharing capability between chips directly determines the overall computing efficiency of the cluster, posing a core bottleneck that constrains the expansion of computing power.