IBM stock jumps ~6% after company unveils sub-1 nanometer chip technology

Markets have not opened yet, but investors are already lining up to take the action on IBM’s stock (NYSE: IBM) as the tech giant revealed what it calls the first chip technology to go under the 1-nanometer technological barrier. 

The news has sent IBM shares up nearly 4% in pre-market trading, a necessary shot in the arm for a stock that had fallen about 11% year-to-date. 

It also represents a major coup for IBM as the semiconductor race shifts to the Moore’s Law lane in response to the traditional method of shrinking transistors running into the proverbial wall.

According to the firm, its new chip has doubled the transistor density it achieved with its 2-nanometer 2021 prototype, fitting roughly 100 billion transistors on a fingernail-sized 0.7-nanometer node (or 7 angstrom). IBM is also projecting that the 2026 chip will outperform the earlier design by up to 50% in computing performance and 70% in energy efficiency.

Why is IBM’s sub-1 nanometer chip a big deal? 

To clear the confusion, IBM’s 0.7-nanometer node does not refer to the physical dimensions of the chip. In fact, node names stopped corresponding to real measurements decades ago. What IBM claims is that its new chip can do what a theoretical chip at that scale can.

IBM introduced the “nanostack” transistor layout as the springboard it used to scale the sub-1 nanometer barrier. Rather than arranging transistors in a single horizontal plane, the design stacks them vertically across two bonded silicon wafers in a staggered pattern. 

The way MIT Technology Review described it, each transistor uses three sheets of silicon, measuring about 15 atoms in thickness and arranged with 9 nanometers of space between them.

Qing Cao, a materials science professor at the University of Illinois at Urbana-Champaign, used the word “transformative” in reaction to how IBM demonstrated stacked transistors on a full production-grade wafer. 

Cao also noted that none of Intel, Samsung, TSMC, and the Belgian research lab Imec had landed on the staggered arrangement before IBM tried it. Notably, it is easier to run wires through this stack compared to ones where the upper layer sits directly above the lower.

When will IBM start selling its new chip? 

IBM licenses its process technology to foundry partners. It does not directly manufacture or sell commercial chips. 

The company told reporters that production could begin within five years, with proper market proliferation another five years away. “Within a decade, this will become another mainstream that we have invented and helped industry to transform,” Bu said during a press briefing.

IBM’s announcement did not include a manufacturing partner for the new sub-1-nanometer process, although Japan’s Rapidus is its current partner on scaling its 2-nanometer technology.

Many industry players are running on that older 2-nanometer nanosheet architecture. TSMC, Samsung, and Intel all use nanosheet-based designs for their current and upcoming chip generations, according to Huiming Bu, vice president of IBM’s semiconductor R&D division.

AI demand has put the crunch on maximizing chip density 

IBM’s announcement is being pitched as the logical technological step forward as AI workloads push existing chip architectures to their limits. According to the company’s research blog, an AI accelerator built with the 7-angstrom process could deliver about seven times what current accelerators achieve.

IBM also reported a 40% improvement in SRAM scaling with the nanostack design, a result presented at the VLSI 2026 symposium. SRAM is the fast on-chip memory that AI inference depends on, and its scaling had stalled in recent chip generations. 

Jay Gambetta, director of IBM Research, said the gap between the 3-nanometer and 2-nanometer generations produced only single-digit percentage improvements in SRAM density.

Dan Hutcheson, vice chair of the analysis firm TechInsights, told MIT Technology Review the nanostack approach “puts another ten, fifteen years on the roadmap” for continued transistor scaling.

Challenges remain. Cao pointed out that stacking layers compounds manufacturing defects: if either tier fails, the entire chip is lost. Thermal management is another constraint, since fabricating the upper layer must not damage the connections beneath it. IBM has kept its method for low-temperature processing confidential.

Investors will be watching IBM’s next earnings call for any indication of licensing discussions.

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